The present disclosure relates generally to data processing and, in particular, to a method, system, and computer program product for two-sided, dynamic cache injection control.
Recently, direct cache access (also referred to as cache injection) schemes have been developed for eliminating costly memory read latency that results from updating invalidated cache lines from memory in a processor complex. For example, if an input/output (I/O) adapter writes a burst of data items to memory and some of these data items are cached in the processor complex, then cache injection strives to directly update cached copies in the processor complex.
Currently, cache injection schemes do not provide efficient management or controls in order to efficiently handle processor complex bandwidth. A processor complex needs interconnect bandwidth to and from the system chipset for operations such as processor pre-fetching, inter-processor communication, cache coherency, cache injection, and most importantly, data transfer. Processor complex interconnect bandwidth is at a premium and should be carefully allocated for a computer system to function. Allowing I/O writes to update cached items using cache injection would reduce memory latency but can hog processor complex bandwidth and starve other transfers detailed above. Similarly, injecting or updating data items into the cache hierarchy of a processor that are not needed by the processor can create cache pollution and directly affect application performance.
What is needed, therefore, is a way to manage cache injection using both I/O hub and I/O adapter resources for efficient use of processor complex interconnect bandwidth and to reduce cache pollution.